At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, and California in the US.
As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with orders of magnitude better energy-efficiency for AI inference at the edge.
At EdgeCortix you will:
Be a part of the team that designs core EdgeCortix technology: Dynamic Neural Accelerator IP for FPGA targets to ensure the best performance and resource utilization, and grow our portfolio of supported FPGA devices further. Work closely with our architecture and compiler teams, engage in performance analysis and improvement activities.
Utilize your deep FPGA expertise to suggest architecture improvements for better resource utilization and place-ability, route-ability, frequency met. Participate in brainstorming the best ways of implementing new features from high-level requirements to micro-architectural tricks. Customize synthesis and implementation flows to ensure high quality of results. Stay up to date with the latest FPGA architectures, and bleeding-edge research on neural network acceleration.
Your day-to-day activities will include the design of high-quality RTL code, developing module-level test benches for your logic, using modern synthesis and implementation tools of major FPGA vendors, committing analysis to identify resource consumption and timing bottlenecks, engaging in system integration activities, engaging in customer-facing analysis and tuning activities.
We are looking for someone who has:
- Bachelor in Computer Science, Electrical Engineering, or similar.
- Strong RTL skills: able to write production-quality readable, maintainable, and synthesizable RTL, debug it, and optimize to achieve desired QoR for particular FPGA architecture. Verilog experience is preferred.
- Extensive experience in implementing high logic utilization designs (70%~90%) on large-scale high-end FPGA devices, while achieving high operation frequencies (300~500MHz).
- Hands-on experience in usage of FPGA toolchains for synthesis, implementation, and timing analysis.
- Experience in writing module-level test benches and running simulations using commercial HDL simulators, such as Xsim, Questa, Xcellium, VCS, or others.
- Experience in FPGA boards bring-up and debugging. Experience in debugging using Integrated Logic Analyzer, Signal Tap, or other signal capture tools.
- Basic programming skills in C++ or C language, experience in writing simple software to test the design on board using the vendor’s SDK.
- Experience using Git for source control and collaborating on complex code-base through a pull-requests/code review flow, such as Github, GitLab, or similar.
Nice to have:
- Master or Ph.D. in Computer Science, Electrical Engineering, or similar with a focus on Computer Architecture, Domain-Specific Architecture, or Parallel Computing.
- Deep technical expertise in modern FPGA architecture of at least one major FPGA vendor. Ability to design RTL that maps efficiently to a specific FPGA architecture, strong understanding, and experience of efficient utilization of special-purpose primitives such as DSP blocks, dedicated interconnect, dedicated data paths around memory blocks, etc. Experience with double pumping.
- Experience in advanced usage of modern Xilinx or Intel FPGA toolchains for synthesis, implementation: logical design partitioning, guiding P&R with placement constraints.
- Hands-on experience in the analysis and fixing of the root cause of timing issues, RTL mapping inefficiencies, undesirable logic optimizations, etc.
- Experience in designing complex algorithmic and compute-intensive IP for applications such as Video Encoding, AI Acceleration, HPC, Databases, Graph Processing Algorithms, and similar.
- Exposure to Chisel or other “Modern HDL” is great. Hands-on experience in projects involving highly parameterizable designs and code generation is an asset.
- Good familiarity with AXI, Avalon MM, Tile Link, or similar on-chip protocols.
- Knowledge of high-speed protocols such as PCIe, DDR, USB, HDMI. Hands-on experience in system design involving the integration of corresponding IPs.
- Experience in automating routine tasks using TCL, Python, Make, etc
- Competitive salary
- Comprehensive paid time off, vacations and sick leaves
- Employee Stock Option Program
- Professional Development Opportunities
- Tons of growth opportunity in a fast paced startup environment.