Design Verification Engineer
At EdgeCortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, EC’s unique Edge AI as a Service platform, hardware aware neural architecture search and chip design capabilities are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices.
As a team, we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling a distributed intelligent edge ecosystem that complements a centralized cloud infrastructure, while keeping data private, enabling real-time computation and the ability to learn continuously from the real-world data. We achieve this by bringing innovative solutions to enterprises, and make edge devices intelligent while optimizing for memory, compute and energy without modifications to existing AI infrastructure and frameworks.
Role and responsibility:
This role is part of the EdgeCortix Artificial Intelligence Hardware Accelerator Team
- Working closely with the design architecture team and contributing to IP, performance and SoC related verification.
- Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
- Writing configurable testbenches in SystemVerilog/UVM and testbench automation.
- Writing System verilog assertions and maintaining them.
- Writing functional coverage and overall functional and code coverage analysis.
- Working on ASIC power estimation and power-aware verification.
- Automating tool flows and creation of result reports.
- 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
- Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification.
- Experience in developing full verification infrastructure from scratch.
- Experience with verification of systems which involve high-speed buses such as AXI4.
- Experience with gate level simulations and delay modeling.
- Experience with constraint random verification.
- Experience with writing functional coverage and overall code coverage analysis.
- Experience with coverage-driven verification methodology.
- Experience in writing and debugging System Verilog assertions.
- Strong experience in debugging RTL and testbenches.
- Prior experience in working with VIPs and verification environments which involve VIPs.
- Prior experience in verifying IPs/systems which include PCI-E/DDR (any) protocol.
- Experience with SoC level verification.
- Experience in using Continuous Integration tools such as Jenkins, Gitlab CI, Circle CI.
- Experience with synthesis tools such as Cadence Genus.
- Experience with power analysis tools such as Cadence Joules.
- Experience with equivalence checking tools such as Cadence Conformal.
- Prior Experience in working with Standard Cell libraries.
- Experience with scripting languages such as perl/python.
Ideal candidate is a person who is personable, self-motivated and has excellent written and verbal communication skills.
What’s in it for you?
Make a difference: you will have the opportunity to join a well-funded startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.
Benefits and Perks
· Competitive salary and stock options
· Flex work time
· Full remote work possibility